%0 Journal Article %1 journals/jssc/Harjani01 %A Harjani, Ramesh %D 2001 %J IEEE J. Solid State Circuits %K dblp %N 6 %P 862-872 %T A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process. %U http://dblp.uni-trier.de/db/journals/jssc/jssc36.html#Harjani01 %V 36

@article{journals/jssc/Harjani01, added-at = {2022-04-06T00:00:00.000+0200}, author = {Harjani, Ramesh}, biburl = {https://www.bibsonomy.org/bibtex/22ce31f6482626e4a7712b6677a4678d7/dblp}, ee = {https://doi.org/10.1109/4.924849}, interhash = {6e019412cc263601cd1865dcb9294a5d}, intrahash = {2ce31f6482626e4a7712b6677a4678d7}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 6, pages = {862-872}, timestamp = {2024-04-08T10:42:49.000+0200}, title = {A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc36.html#Harjani01}, volume = 36, year = 2001 }