%0 Journal Article %1 journals/tcad/PlasVGS02 %A der Plas, Geert Van %A Vandenbussche, Jan %A Gielen, Georges G. E. %A Sansen, Willy M. C. %D 2002 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 6 %P 645-661 %T A layout synthesis methodology for array-type analog blocks. %U http://dblp.uni-trier.de/db/journals/tcad/tcad21.html#PlasVGS02 %V 21

@article{journals/tcad/PlasVGS02, added-at = {2020-09-24T00:00:00.000+0200}, author = {der Plas, Geert Van and Vandenbussche, Jan and Gielen, Georges G. E. and Sansen, Willy M. C.}, biburl = {https://www.bibsonomy.org/bibtex/2b2a8731c816528d176a7b99a29f0d339/dblp}, ee = {https://doi.org/10.1109/TCAD.2002.1004309}, interhash = {6ef721a3f2b1eb487e8bfb66eb23efdd}, intrahash = {b2a8731c816528d176a7b99a29f0d339}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 6, pages = {645-661}, timestamp = {2020-09-25T11:46:34.000+0200}, title = {A layout synthesis methodology for array-type analog blocks.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad21.html#PlasVGS02}, volume = 21, year = 2002 }