%0 Journal Article %1 journals/integration/El-MalehT21 %A El-Maleh, Aiman H. %A Talib, Ghashmi H. Bin %D 2021 %J Integr. %K dblp %P 49-59 %T Time redundancy and gate sizing soft error-tolerant based adder design. %U http://dblp.uni-trier.de/db/journals/integration/integration78.html#El-MalehT21 %V 78

@article{journals/integration/El-MalehT21, added-at = {2021-10-14T00:00:00.000+0200}, author = {El-Maleh, Aiman H. and Talib, Ghashmi H. Bin}, biburl = {https://www.bibsonomy.org/bibtex/2679250d66ac3563137dd0ab480e90f49/dblp}, ee = {https://doi.org/10.1016/j.vlsi.2021.01.001}, interhash = {704c4c50b1624079acb11a662935a7eb}, intrahash = {679250d66ac3563137dd0ab480e90f49}, journal = {Integr.}, keywords = {dblp}, pages = {49-59}, timestamp = {2024-04-08T13:15:02.000+0200}, title = {Time redundancy and gate sizing soft error-tolerant based adder design.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration78.html#El-MalehT21}, volume = 78, year = 2021 }