%0 Conference Paper %1 conf/ets/KajiharaSR04 %A Kajihara, Seiji %A Saluja, Kewal K. %A Reddy, Sudhakar M. %B ETS %D 2004 %I IEEE Computer Society %K dblp %P 108-113 %T Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. %U http://dblp.uni-trier.de/db/conf/ets/ets2004.html#KajiharaSR04 %@ 0-7695-2119-3

@inproceedings{conf/ets/KajiharaSR04, added-at = {2023-03-23T00:00:00.000+0100}, author = {Kajihara, Seiji and Saluja, Kewal K. and Reddy, Sudhakar M.}, biburl = {https://www.bibsonomy.org/bibtex/25b8dcf8bb1b7f46c26204059606223b5/dblp}, booktitle = {ETS}, crossref = {conf/ets/2004}, ee = {https://doi.ieeecomputersociety.org/10.1109/ETSYM.2004.1347620}, interhash = {70b9a58871aa1edd9c795120f9f4cd62}, intrahash = {5b8dcf8bb1b7f46c26204059606223b5}, isbn = {0-7695-2119-3}, keywords = {dblp}, pages = {108-113}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T20:47:59.000+0200}, title = {Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.}, url = {http://dblp.uni-trier.de/db/conf/ets/ets2004.html#KajiharaSR04}, year = 2004 }