%0 Journal Article %1 journals/tcad/QianPP94 %A Qian, Jessica %A Pullela, Satyamurthy %A Pillage, Lawrence T. %D 1994 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 12 %P 1526-1535 %T Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. %U http://dblp.uni-trier.de/db/journals/tcad/tcad13.html#QianPP94 %V 13

@article{journals/tcad/QianPP94, added-at = {2020-09-24T00:00:00.000+0200}, author = {Qian, Jessica and Pullela, Satyamurthy and Pillage, Lawrence T.}, biburl = {https://www.bibsonomy.org/bibtex/2fe1cccef04609c74a918fbe33e7d421a/dblp}, ee = {https://doi.org/10.1109/43.331409}, interhash = {774f7e5ca01351b9a496fe5cd0117ea4}, intrahash = {fe1cccef04609c74a918fbe33e7d421a}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 12, pages = {1526-1535}, timestamp = {2020-09-25T11:47:15.000+0200}, title = {Modeling the "Effective capacitance" for the RC interconnect of CMOS gates.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad13.html#QianPP94}, volume = 13, year = 1994 }