%0 Journal Article %1 journals/jssc/DomerFR95 %A Domer, Steven M. %A Foertsch, Samuel A. %A Raskin, Glenn D. %D 1995 %J IEEE J. Solid State Circuits %K dblp %N 3 %P 286-294 %T Model for yield and manufacturing prediction on VLSI designs for advanced technologies, mixed circuitry, and memories. %U http://dblp.uni-trier.de/db/journals/jssc/jssc30.html#DomerFR95 %V 30

@article{journals/jssc/DomerFR95, added-at = {2023-05-03T00:00:00.000+0200}, author = {Domer, Steven M. and Foertsch, Samuel A. and Raskin, Glenn D.}, biburl = {https://www.bibsonomy.org/bibtex/290ab809188a8f0e87bfc71aa7d09b1e8/dblp}, ee = {https://doi.org/10.1109/4.364443}, interhash = {7797ab1f674f23a9ce937c8c788fed5e}, intrahash = {90ab809188a8f0e87bfc71aa7d09b1e8}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, month = {March}, number = 3, pages = {286-294}, timestamp = {2024-04-08T10:44:01.000+0200}, title = {Model for yield and manufacturing prediction on VLSI designs for advanced technologies, mixed circuitry, and memories.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc30.html#DomerFR95}, volume = 30, year = 1995 }