%0 Journal Article %1 journals/et/BonhommeGGLPV06 %A Bonhomme, Yannick %A Girard, Patrick %A Guiller, Loïs %A Landrault, Christian %A Pravossoudovitch, Serge %A Virazel, Arnaud %D 2006 %J J. Electron. Test. %K dblp %N 1 %P 89-99 %T A Gated Clock Scheme for Low Power Testing of Logic Cores. %U http://dblp.uni-trier.de/db/journals/et/et22.html#BonhommeGGLPV06 %V 22

@article{journals/et/BonhommeGGLPV06, added-at = {2023-03-21T00:00:00.000+0100}, author = {Bonhomme, Yannick and Girard, Patrick and Guiller, Loïs and Landrault, Christian and Pravossoudovitch, Serge and Virazel, Arnaud}, biburl = {https://www.bibsonomy.org/bibtex/29d5e10427b10eed262f69466d18e2827/dblp}, ee = {https://doi.org/10.1007/s10836-006-6259-1}, interhash = {781b7757af7e4adb2de8c440d7e3c3de}, intrahash = {9d5e10427b10eed262f69466d18e2827}, journal = {J. Electron. Test.}, keywords = {dblp}, number = 1, pages = {89-99}, timestamp = {2024-04-08T20:52:46.000+0200}, title = {A Gated Clock Scheme for Low Power Testing of Logic Cores.}, url = {http://dblp.uni-trier.de/db/journals/et/et22.html#BonhommeGGLPV06}, volume = 22, year = 2006 }