%0 Conference Paper %1 conf/isvlsi/WilleZD11 %A Wille, Robert %A Zhang, Hongyan %A Drechsler, Rolf %B ISVLSI %D 2011 %I IEEE Computer Society %K %P 120-125 %T ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2011.html#WilleZD11 %@ 978-0-7695-4447-2

@inproceedings{conf/isvlsi/WilleZD11, added-at = {2023-12-13T01:55:26.000+0100}, author = {Wille, Robert and Zhang, Hongyan and Drechsler, Rolf}, biburl = {https://www.bibsonomy.org/bibtex/27ab3f509d394122215a5f0d64e0d80b7/admin}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2011}, ee = {https://www.wikidata.org/entity/Q59242519}, interhash = {785b612a350ca23c77a3a5c751d23256}, intrahash = {7ab3f509d394122215a5f0d64e0d80b7}, isbn = {978-0-7695-4447-2}, keywords = {}, pages = {120-125}, publisher = {IEEE Computer Society}, timestamp = {2023-12-13T01:55:26.000+0100}, title = {ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2011.html#WilleZD11}, year = 2011 }