Inproceedings,
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, M. Yoshimoto, and T. Matsuno.VLSI-SoC, page 192-197. IEEE, (2006)
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- inproceedings
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- VLSI-SoC
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- 2006
- pages
- 192-197
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- IEEE
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- ee
- https://doi.org/10.1109/VLSISOC.2006.313232
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%1 conf/vlsi/MiyakoshiMHIIKYM06
%A Miyakoshi, Junichi
%A Murachi, Yuichiro
%A Hamamoto, Masaki
%A Iinuma, Takahiro
%A Ishihara, Tomokazu
%A Kawaguchi, Hiroshi
%A Yoshimoto, Masahiko
%A Matsuno, Tetsuro
%B VLSI-SoC
%D 2006
%I IEEE
%K dblp
%P 192-197
%T A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
%U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2006.html#MiyakoshiMHIIKYM06
@inproceedings{conf/vlsi/MiyakoshiMHIIKYM06,
added-at = {2024-03-11T00:00:00.000+0100},
author = {Miyakoshi, Junichi and Murachi, Yuichiro and Hamamoto, Masaki and Iinuma, Takahiro and Ishihara, Tomokazu and Kawaguchi, Hiroshi and Yoshimoto, Masahiko and Matsuno, Tetsuro},
biburl = {https://www.bibsonomy.org/bibtex/288699b787798d0dea58d54416ac23f46/dblp},
booktitle = {VLSI-SoC},
crossref = {conf/vlsi/2006soc},
ee = {https://doi.org/10.1109/VLSISOC.2006.313232},
interhash = {79affa12e3bfe51c2fafb0a201baf4cf},
intrahash = {88699b787798d0dea58d54416ac23f46},
keywords = {dblp},
pages = {192-197},
publisher = {IEEE},
timestamp = {2024-04-10T16:40:24.000+0200},
title = {A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.},
url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2006.html#MiyakoshiMHIIKYM06},
year = 2006
}