%0 Conference Paper %1 conf/icassp/ChiP02 %A Chi, Zhipei %A Parhi, Keshab K. %B ICASSP %D 2002 %I IEEE %K dblp %P 3089-3092 %T High speed algorithm and VLSI architecture design for decoding BCH product codes. %U http://dblp.uni-trier.de/db/conf/icassp/icassp2002.html#ChiP02 %@ 0-7803-7402-9

@inproceedings{conf/icassp/ChiP02, added-at = {2017-05-19T00:00:00.000+0200}, author = {Chi, Zhipei and Parhi, Keshab K.}, biburl = {https://www.bibsonomy.org/bibtex/2ee12b7e87cae46a97c522ba7936da41c/dblp}, booktitle = {ICASSP}, crossref = {conf/icassp/2002}, ee = {https://doi.org/10.1109/ICASSP.2002.5745302}, interhash = {7ac1097d491a2f9cb57caa87c1a96290}, intrahash = {ee12b7e87cae46a97c522ba7936da41c}, isbn = {0-7803-7402-9}, keywords = {dblp}, pages = {3089-3092}, publisher = {IEEE}, timestamp = {2019-10-17T17:30:12.000+0200}, title = {High speed algorithm and VLSI architecture design for decoding BCH product codes.}, url = {http://dblp.uni-trier.de/db/conf/icassp/icassp2002.html#ChiP02}, year = 2002 }