%0 Journal Article %1 journals/todaes/KimKS16 %A Kim, Sangmin %A Kang, Seokhyeong %A Shin, Youngsoo %D 2016 %J ACM Trans. Design Autom. Electr. Syst. %K dblp %N 3 %P 51:1-51:23 %T Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. %U http://dblp.uni-trier.de/db/journals/todaes/todaes21.html#KimKS16 %V 21

@article{journals/todaes/KimKS16, added-at = {2018-11-06T00:00:00.000+0100}, author = {Kim, Sangmin and Kang, Seokhyeong and Shin, Youngsoo}, biburl = {https://www.bibsonomy.org/bibtex/28a19467418c5ab085e82fb70a0c2532e/dblp}, ee = {https://doi.org/10.1145/2856032}, interhash = {7b0de22c052ef9b21de00f08ae6bdd11}, intrahash = {8a19467418c5ab085e82fb70a0c2532e}, journal = {ACM Trans. Design Autom. Electr. Syst.}, keywords = {dblp}, number = 3, pages = {51:1-51:23}, timestamp = {2018-11-07T12:24:07.000+0100}, title = {Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization.}, url = {http://dblp.uni-trier.de/db/journals/todaes/todaes21.html#KimKS16}, volume = 21, year = 2016 }