%0 Conference Paper %1 conf/vlsid/SheshadriAA13 %A Sheshadri, Vijay %A Agrawal, Vishwani D. %A Agrawal, Prathima %B VLSI Design %D 2013 %I IEEE Computer Society %K dblp %P 267-272 %T Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#SheshadriAA13 %@ 978-1-4673-4639-9

@inproceedings{conf/vlsid/SheshadriAA13, added-at = {2023-03-24T00:00:00.000+0100}, author = {Sheshadri, Vijay and Agrawal, Vishwani D. and Agrawal, Prathima}, biburl = {https://www.bibsonomy.org/bibtex/266e19408bcab1e979af0f34c782b509a/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2013}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2013.199}, interhash = {7c1ac1a04864ba3d51eb758a7e445ad4}, intrahash = {66e19408bcab1e979af0f34c782b509a}, isbn = {978-1-4673-4639-9}, keywords = {dblp}, pages = {267-272}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:08:28.000+0200}, title = {Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#SheshadriAA13}, year = 2013 }