%0 Journal Article %1 journals/vlsi/JainG16 %A Jain, Abhishek %A Gupta, Richa %D 2016 %J VLSI Design %K dblp %P 7283471:1-7283471:14 %T Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi2016.html#JainG16 %V 2016

@article{journals/vlsi/JainG16, added-at = {2021-10-14T00:00:00.000+0200}, author = {Jain, Abhishek and Gupta, Richa}, biburl = {https://www.bibsonomy.org/bibtex/2ad2558e8e565d042452b4ad5f43474e5/dblp}, ee = {https://www.wikidata.org/entity/Q59142356}, interhash = {7c4326d7065913b6873acff067869f24}, intrahash = {ad2558e8e565d042452b4ad5f43474e5}, journal = {VLSI Design}, keywords = {dblp}, pages = {7283471:1-7283471:14}, timestamp = {2024-04-08T12:07:12.000+0200}, title = {Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi2016.html#JainG16}, volume = 2016, year = 2016 }