%0 Conference Paper %1 conf/ivsw/SinglaLG19 %A Singla, Aayush %A Lippmann, Bernhard %A Graeb, Helmut %B IVSW %D 2019 %I IEEE %K dblp %P 55-60 %T Verification of Physical Chip Layouts Using GDSII Design Data. %U http://dblp.uni-trier.de/db/conf/ivsw/ivsw2019.html#SinglaLG19 %@ 978-1-7281-2671-5

@inproceedings{conf/ivsw/SinglaLG19, added-at = {2019-10-08T00:00:00.000+0200}, author = {Singla, Aayush and Lippmann, Bernhard and Graeb, Helmut}, biburl = {https://www.bibsonomy.org/bibtex/2e2ab84a28f577dee2286afa353d34f0c/dblp}, booktitle = {IVSW}, crossref = {conf/ivsw/2019}, ee = {https://doi.org/10.1109/IVSW.2019.8854432}, interhash = {7cb217b2aed1645d897cb5e9267af781}, intrahash = {e2ab84a28f577dee2286afa353d34f0c}, isbn = {978-1-7281-2671-5}, keywords = {dblp}, pages = {55-60}, publisher = {IEEE}, timestamp = {2019-10-17T18:38:46.000+0200}, title = {Verification of Physical Chip Layouts Using GDSII Design Data.}, url = {http://dblp.uni-trier.de/db/conf/ivsw/ivsw2019.html#SinglaLG19}, year = 2019 }