%0 Conference Paper %1 conf/icetet/KumarPR10 %A Kumar, A. Ravi %A homepages/07/10139, %A Reddy, G. M. Sree Rama %B ICETET %D 2010 %I IEEE Computer Society %K dblp %P 770-775 %T Design and Verification of Cache Memory Decoder for High Speed Multicore Processor. %U http://dblp.uni-trier.de/db/conf/icetet/icetet2010.html#KumarPR10 %@ 978-0-7695-4246-1

@inproceedings{conf/icetet/KumarPR10, added-at = {2017-09-11T00:00:00.000+0200}, author = {Kumar, A. Ravi and homepages/07/10139 and Reddy, G. M. Sree Rama}, biburl = {https://www.bibsonomy.org/bibtex/2548670146766f7ee55c235cd7e035df0/dblp}, booktitle = {ICETET}, crossref = {conf/icetet/2010}, ee = {http://doi.ieeecomputersociety.org/10.1109/ICETET.2010.40}, interhash = {17f68b8365e7ca53f6bff70007835854}, intrahash = {548670146766f7ee55c235cd7e035df0}, isbn = {978-0-7695-4246-1}, keywords = {dblp}, pages = {770-775}, publisher = {IEEE Computer Society}, timestamp = {2017-09-12T11:39:05.000+0200}, title = {Design and Verification of Cache Memory Decoder for High Speed Multicore Processor.}, url = {http://dblp.uni-trier.de/db/conf/icetet/icetet2010.html#KumarPR10}, year = 2010 }