%0 Journal Article %1 journals/jssc/SunRPKLJS19 %A Sun, Xun %A ur Rahman, Fahim %A Pamula, Venkata Rajesh %A Kim, Sung %A Li, Xi %A John, Naveen %A Sathe, Visvesh S. %D 2019 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 3215-3225 %T An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. %U http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#SunRPKLJS19 %V 54

@article{journals/jssc/SunRPKLJS19, added-at = {2020-08-30T00:00:00.000+0200}, author = {Sun, Xun and ur Rahman, Fahim and Pamula, Venkata Rajesh and Kim, Sung and Li, Xi and John, Naveen and Sathe, Visvesh S.}, biburl = {https://www.bibsonomy.org/bibtex/292558617c0b0c4fef21ecb77f404cbdd/dblp}, ee = {https://doi.org/10.1109/JSSC.2019.2936968}, interhash = {8104f10336fe30fa08ab021f57e5a31c}, intrahash = {92558617c0b0c4fef21ecb77f404cbdd}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {3215-3225}, timestamp = {2020-08-31T11:40:44.000+0200}, title = {An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#SunRPKLJS19}, volume = 54, year = 2019 }