%0 Journal Article %1 journals/ijrc/JaquenodVS14 %A Jaquenod, Guillermo A. %A Valls, Javier %A Siman, Javier %D 2014 %J Int. J. Reconfigurable Comput. %K dblp %P 546264:1-546264:5 %T Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. %U http://dblp.uni-trier.de/db/journals/ijrc/ijrc2014.html#JaquenodVS14 %V 2014

@article{journals/ijrc/JaquenodVS14, added-at = {2020-04-02T00:00:00.000+0200}, author = {Jaquenod, Guillermo A. and Valls, Javier and Siman, Javier}, biburl = {https://www.bibsonomy.org/bibtex/2f5926f5aa21534dbc61c362a58f9eee7/dblp}, ee = {https://www.wikidata.org/entity/Q59046541}, interhash = {85bd38edad5bc2371c7d49bb92f4536a}, intrahash = {f5926f5aa21534dbc61c362a58f9eee7}, journal = {Int. J. Reconfigurable Comput.}, keywords = {dblp}, pages = {546264:1-546264:5}, timestamp = {2020-04-03T11:41:01.000+0200}, title = {Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain.}, url = {http://dblp.uni-trier.de/db/journals/ijrc/ijrc2014.html#JaquenodVS14}, volume = 2014, year = 2014 }