%0 Conference Paper %1 conf/fpl/LawalTO05 %A Lawal, Najeem %A Thörnberg, Benny %A O'Nils, Mattias %B FPL %D 2005 %E Rissa, Tero %E Wilton, Steven J. E. %E Leong, Philip Heng Wai %I IEEE %K dblp %P 136-141 %T Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#LawalTO05 %@ 0-7803-9362-7

@inproceedings{conf/fpl/LawalTO05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Lawal, Najeem and Thörnberg, Benny and O'Nils, Mattias}, biburl = {https://www.bibsonomy.org/bibtex/2c7490189bec391b91745fc2bbdbfbf92/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2005}, editor = {Rissa, Tero and Wilton, Steven J. E. and Leong, Philip Heng Wai}, ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515712}, interhash = {8666affe4c0fe1acb3e6f925f07a82e9}, intrahash = {c7490189bec391b91745fc2bbdbfbf92}, isbn = {0-7803-9362-7}, keywords = {dblp}, pages = {136-141}, publisher = {IEEE}, timestamp = {2024-04-10T14:52:35.000+0200}, title = {Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2005.html#LawalTO05}, year = 2005 }