%0 Journal Article %1 journals/jcp/NaviKRSMD08 %A Navi, Keivan %A Kavehei, Omid %A Rouholamini, Mahnoush %A Sahafi, Amir %A Mehrabi, Shima %A Dadkhahi, Nooshin %D 2008 %J J. Comput. %K dblp %N 2 %P 48-54 %T Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell. %U http://dblp.uni-trier.de/db/journals/jcp/jcp3.html#NaviKRSMD08 %V 3

@article{journals/jcp/NaviKRSMD08, added-at = {2021-10-14T00:00:00.000+0200}, author = {Navi, Keivan and Kavehei, Omid and Rouholamini, Mahnoush and Sahafi, Amir and Mehrabi, Shima and Dadkhahi, Nooshin}, biburl = {https://www.bibsonomy.org/bibtex/2aa79b2819fb83589389260186fe4b0f7/dblp}, ee = {https://doi.org/10.4304/jcp.3.2.48-54}, interhash = {875f2c5e34eb263d8c65ef91753faa70}, intrahash = {aa79b2819fb83589389260186fe4b0f7}, journal = {J. Comput.}, keywords = {dblp}, number = 2, pages = {48-54}, timestamp = {2024-04-09T06:16:48.000+0200}, title = {Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell.}, url = {http://dblp.uni-trier.de/db/journals/jcp/jcp3.html#NaviKRSMD08}, volume = 3, year = 2008 }