%0 Journal Article %1 journals/ieicet/ShiehWW08 %A Shieh, Ming-Der %A Wang, Tai-Ping %A Wu, Chien-Ming %D 2008 %J IEICE Trans. Inf. Syst. %K dblp %N 9 %P 2300-2311 %T Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet91d.html#ShiehWW08 %V 91-D

@article{journals/ieicet/ShiehWW08, added-at = {2020-04-11T00:00:00.000+0200}, author = {Shieh, Ming-Der and Wang, Tai-Ping and Wu, Chien-Ming}, biburl = {https://www.bibsonomy.org/bibtex/2ab0e2d5efd20770c2b910e0293221dff/dblp}, ee = {https://doi.org/10.1093/ietisy/e91-d.9.2300}, interhash = {88304f335c408a524a30d9a18831b1d3}, intrahash = {ab0e2d5efd20770c2b910e0293221dff}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 9, pages = {2300-2311}, timestamp = {2020-04-14T11:45:14.000+0200}, title = {Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet91d.html#ShiehWW08}, volume = {91-D}, year = 2008 }