%0 Journal Article %1 journals/tcasII/HuangHWYZZYL22 %A Huang, Yuxuan %A He, Yifan %A Wang, Jingyu %A Yue, Jinshan %A Zhang, Lu %A Zou, Kaiwei %A Yang, Huazhong %A Liu, Yongpan %D 2022 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 7 %P 3144-3148 %T Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII69.html#HuangHWYZZYL22 %V 69

@article{journals/tcasII/HuangHWYZZYL22, added-at = {2022-07-25T00:00:00.000+0200}, author = {Huang, Yuxuan and He, Yifan and Wang, Jingyu and Yue, Jinshan and Zhang, Lu and Zou, Kaiwei and Yang, Huazhong and Liu, Yongpan}, biburl = {https://www.bibsonomy.org/bibtex/21a3ad5beb9de091e2d13adf93acb2b50/dblp}, ee = {https://doi.org/10.1109/TCSII.2022.3163177}, interhash = {888ecef3cebf2fc5091d10e07c21e795}, intrahash = {1a3ad5beb9de091e2d13adf93acb2b50}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 7, pages = {3144-3148}, timestamp = {2024-04-08T16:52:44.000+0200}, title = {Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII69.html#HuangHWYZZYL22}, volume = 69, year = 2022 }