%0 Conference Paper %1 conf/fpga/HuttonRC97 %A Hutton, Michael D. %A Rose, Jonathan %A Corneil, Derek G. %B FPGA %D 1997 %E Ebeling, Carl %I ACM %K dblp %P 149-155 %T Generation of Synthetic Sequential Benchmark Circuits. %U http://dblp.uni-trier.de/db/conf/fpga/fpga97.html#HuttonRC97 %@ 0-89791-801-0

@inproceedings{conf/fpga/HuttonRC97, added-at = {2017-02-02T00:00:00.000+0100}, author = {Hutton, Michael D. and Rose, Jonathan and Corneil, Derek G.}, biburl = {https://www.bibsonomy.org/bibtex/2e69b18ab27519ef0c96750a2c4909071/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/1997}, editor = {Ebeling, Carl}, ee = {http://doi.acm.org/10.1145/258305.258333}, interhash = {8a0e1fcd54993e679508a3bf2b92291c}, intrahash = {e69b18ab27519ef0c96750a2c4909071}, isbn = {0-89791-801-0}, keywords = {dblp}, pages = {149-155}, publisher = {ACM}, timestamp = {2017-02-03T11:36:31.000+0100}, title = {Generation of Synthetic Sequential Benchmark Circuits.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga97.html#HuttonRC97}, year = 1997 }