%0 Conference Paper %1 conf/vlsid/Agrawal00 %A Agrawal, Vishwani D. %B VLSI Design %D 2000 %I IEEE Computer Society %K dblp %P 306-311 %T Choice of Tests for Logic Verification and Equivalence Checking. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#Agrawal00 %@ 0-7695-0487-6

@inproceedings{conf/vlsid/Agrawal00, added-at = {2023-03-24T00:00:00.000+0100}, author = {Agrawal, Vishwani D.}, biburl = {https://www.bibsonomy.org/bibtex/2caca7ebdb0db66fba3604cacdb516882/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2000}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812626}, interhash = {8c1eb68bb2c2daa6682f96b5b3bef44c}, intrahash = {caca7ebdb0db66fba3604cacdb516882}, isbn = {0-7695-0487-6}, keywords = {dblp}, pages = {306-311}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:01.000+0200}, title = {Choice of Tests for Logic Verification and Equivalence Checking.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#Agrawal00}, year = 2000 }