Inproceedings,

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique.

, , , , , , , and .
ISSCC, page 1-3. IEEE, (2015)

Meta data

Tags

Users

  • @dblp

Comments and Reviews