%0 Conference Paper %1 conf/iscas/RahmanC04 %A Rahman, Hafijur %A Chakrabarti, Chaitali %B ISCAS (2) %D 2004 %I IEEE %K %P 297-300 %T A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#RahmanC04 %@ 0-7803-8251-X

@inproceedings{conf/iscas/RahmanC04, added-at = {2023-12-13T03:41:39.000+0100}, author = {Rahman, Hafijur and Chakrabarti, Chaitali}, biburl = {https://www.bibsonomy.org/bibtex/27028838d1dc1c4866500eb3ccb278035/admin}, booktitle = {ISCAS (2)}, crossref = {conf/iscas/2004}, ee = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255}, interhash = {8dec7aea55dfbf6a4378dbac978777e7}, intrahash = {7028838d1dc1c4866500eb3ccb278035}, isbn = {0-7803-8251-X}, keywords = {}, pages = {297-300}, publisher = {IEEE}, timestamp = {2023-12-13T03:41:39.000+0100}, title = {A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#RahmanC04}, year = 2004 }