%0 Journal Article %1 journals/ieicet/BlockM17 %A Block, Henry %A Maruyama, Tsutomu %D 2017 %J IEICE Trans. Inf. Syst. %K dblp %N 2 %P 256-264 %T FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet100d.html#BlockM17 %V 100-D

@article{journals/ieicet/BlockM17, added-at = {2020-04-11T00:00:00.000+0200}, author = {Block, Henry and Maruyama, Tsutomu}, biburl = {https://www.bibsonomy.org/bibtex/2d0cc073e5b813cb68d61a6f2488b96cd/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e100-d_2_256}, interhash = {18ec42703eb3d95c2dea43e2d4f392e9}, intrahash = {d0cc073e5b813cb68d61a6f2488b96cd}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 2, pages = {256-264}, timestamp = {2020-04-14T11:42:16.000+0200}, title = {FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet100d.html#BlockM17}, volume = {100-D}, year = 2017 }