%0 Journal Article %1 journals/cee/LakshmiD11 %A Lakshmi, Boppana %A Dhar, A. S. %D 2011 %J Comput. Electr. Eng. %K dblp %N 6 %P 1032-1042 %T VLSI architecture for low latency radix-4 CORDIC. %U http://dblp.uni-trier.de/db/journals/cee/cee37.html#LakshmiD11 %V 37

@article{journals/cee/LakshmiD11, added-at = {2022-07-06T00:00:00.000+0200}, author = {Lakshmi, Boppana and Dhar, A. S.}, biburl = {https://www.bibsonomy.org/bibtex/2851aac369ed33918cdf67fc575ddd0f9/dblp}, ee = {https://doi.org/10.1016/j.compeleceng.2011.07.011}, interhash = {92e99cbb036b51512d9f00e64f19c3c8}, intrahash = {851aac369ed33918cdf67fc575ddd0f9}, journal = {Comput. Electr. Eng.}, keywords = {dblp}, number = 6, pages = {1032-1042}, timestamp = {2024-04-08T18:53:35.000+0200}, title = {VLSI architecture for low latency radix-4 CORDIC.}, url = {http://dblp.uni-trier.de/db/journals/cee/cee37.html#LakshmiD11}, volume = 37, year = 2011 }