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- BibTeX key
- conf/icecsys/SrivastavRSMTYG21
- entry type
- inproceedings
- booktitle
- ICECS
- year
- 2021
- pages
- 1-6
- publisher
- IEEE
- crossref
- conf/icecsys/2021
- ee
- https://doi.org/10.1109/ICECS53924.2021.9665552
- isbn
- 978-1-7281-8281-0
- url
- http://dblp.uni-trier.de/db/conf/icecsys/icecsys2021.html#SrivastavRSMTYG21
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- please select -%0 Conference Paper
%1 conf/icecsys/SrivastavRSMTYG21
%A Srivastav, Mukesh Kumar
%A Rimjhim,
%A Soni, Govind
%A Mittal, Umang
%A Tewari, Rupali
%A Yadav, Riya
%A Grover, Anuj
%A Dhori, Kedar Janardan
%A Rawat, Harsh
%B ICECS
%D 2021
%I IEEE
%K dblp
%P 1-6
%T Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.
%U http://dblp.uni-trier.de/db/conf/icecsys/icecsys2021.html#SrivastavRSMTYG21
%@ 978-1-7281-8281-0
@inproceedings{conf/icecsys/SrivastavRSMTYG21,
added-at = {2022-01-14T00:00:00.000+0100},
author = {Srivastav, Mukesh Kumar and Rimjhim and Soni, Govind and Mittal, Umang and Tewari, Rupali and Yadav, Riya and Grover, Anuj and Dhori, Kedar Janardan and Rawat, Harsh},
biburl = {https://www.bibsonomy.org/bibtex/22e19a9a9ec4623df730d0b792824dca8/dblp},
booktitle = {ICECS},
crossref = {conf/icecsys/2021},
ee = {https://doi.org/10.1109/ICECS53924.2021.9665552},
interhash = {93b16c24802cfbc621f1b07828f7746e},
intrahash = {2e19a9a9ec4623df730d0b792824dca8},
isbn = {978-1-7281-8281-0},
keywords = {dblp},
pages = {1-6},
publisher = {IEEE},
timestamp = {2024-04-09T16:20:33.000+0200},
title = {Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.},
url = {http://dblp.uni-trier.de/db/conf/icecsys/icecsys2021.html#SrivastavRSMTYG21},
year = 2021
}