%0 Journal Article %1 journals/tcas/Ning20 %A Ning, Sheyang %D 2020 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 10 %P 2164-2168 %T Improving Resistive RAM Hard and Soft Decision Correctable BERs by Using Improved-LLR and Reset-Check-Reverse-Flag Concatenating LDPC Code. %U http://dblp.uni-trier.de/db/journals/tcas/tcasII67.html#Ning20 %V 67-II

@article{journals/tcas/Ning20, added-at = {2020-10-08T00:00:00.000+0200}, author = {Ning, Sheyang}, biburl = {https://www.bibsonomy.org/bibtex/29c55a6eda3119b5bc1d3f0d69a9b67af/dblp}, ee = {https://doi.org/10.1109/TCSII.2019.2960484}, interhash = {9af141ede365f442934a098afb33ee43}, intrahash = {9c55a6eda3119b5bc1d3f0d69a9b67af}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 10, pages = {2164-2168}, timestamp = {2020-10-09T11:38:18.000+0200}, title = {Improving Resistive RAM Hard and Soft Decision Correctable BERs by Using Improved-LLR and Reset-Check-Reverse-Flag Concatenating LDPC Code.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII67.html#Ning20}, volume = {67-II}, year = 2020 }