%0 Conference Paper %1 conf/iscc/TangSJYB16 %A Tang, Qiu %A Su, Majing %A Jiang, Lei %A Yang, Jiajia %A Bai, Xu %B ISCC %D 2016 %I IEEE Computer Society %K %P 597-603 %T A scalable architecture for low-latency market-data processing on FPGA. %U http://dblp.uni-trier.de/db/conf/iscc/iscc2016.html#TangSJYB16 %@ 978-1-5090-0679-3

@inproceedings{conf/iscc/TangSJYB16, added-at = {2023-12-13T05:06:27.000+0100}, author = {Tang, Qiu and Su, Majing and Jiang, Lei and Yang, Jiajia and Bai, Xu}, biburl = {https://www.bibsonomy.org/bibtex/2cea94e3f804a93fe9e5da3268d4a3148/admin}, booktitle = {ISCC}, crossref = {conf/iscc/2016}, ee = {http://doi.ieeecomputersociety.org/10.1109/ISCC.2016.7543802}, interhash = {9e8203aa791e8881277d546b3eff2d1b}, intrahash = {cea94e3f804a93fe9e5da3268d4a3148}, isbn = {978-1-5090-0679-3}, keywords = {}, pages = {597-603}, publisher = {IEEE Computer Society}, timestamp = {2023-12-13T05:06:27.000+0100}, title = {A scalable architecture for low-latency market-data processing on FPGA.}, url = {http://dblp.uni-trier.de/db/conf/iscc/iscc2016.html#TangSJYB16}, year = 2016 }