%0 Conference Paper %1 conf/fpl/GortA11 %A Gort, Marcel %A Anderson, Jason Helge %B FPL %D 2011 %I IEEE Computer Society %K dblp %P 336-342 %T Reducing FPGA Router Run-Time through Algorithm and Architecture. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#GortA11 %@ 978-1-4577-1484-9

@inproceedings{conf/fpl/GortA11, added-at = {2023-03-24T00:00:00.000+0100}, author = {Gort, Marcel and Anderson, Jason Helge}, biburl = {https://www.bibsonomy.org/bibtex/20c781ccf7d190c199a4b212fde849cca/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2011}, ee = {https://doi.ieeecomputersociety.org/10.1109/FPL.2011.67}, interhash = {9f9e9e1d54173a5d84b87846c03fc8b0}, intrahash = {0c781ccf7d190c199a4b212fde849cca}, isbn = {978-1-4577-1484-9}, keywords = {dblp}, pages = {336-342}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T14:51:39.000+0200}, title = {Reducing FPGA Router Run-Time through Algorithm and Architecture.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2011.html#GortA11}, year = 2011 }