%0 Journal Article %1 journals/tcas/ChenSZ15 %A Chen, Chia-Hsiang %A Song, Shiming %A Zhang, Zhengya %D 2015 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 5 %P 471-475 %T An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation. %U http://dblp.uni-trier.de/db/journals/tcas/tcasII62.html#ChenSZ15 %V 62-II

@article{journals/tcas/ChenSZ15, added-at = {2022-12-07T00:00:00.000+0100}, author = {Chen, Chia-Hsiang and Song, Shiming and Zhang, Zhengya}, biburl = {https://www.bibsonomy.org/bibtex/216817d9c195b9cf874949c7792077bce/dblp}, ee = {https://doi.org/10.1109/TCSII.2014.2386251}, interhash = {a0edf2f9f0e1f512e261d830a67cb214}, intrahash = {16817d9c195b9cf874949c7792077bce}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 5, pages = {471-475}, timestamp = {2024-04-09T06:12:55.000+0200}, title = {An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII62.html#ChenSZ15}, volume = {62-II}, year = 2015 }