%0 Conference Paper %1 conf/ismvl/DatlaTHH09 %A Datla, Satyendra R. %A Thornton, Mitchell A. %A Hendrix, Luther %A Henderson, Dave %B ISMVL %D 2009 %I IEEE Computer Society %K dblp %P 256-261 %T Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. %U http://dblp.uni-trier.de/db/conf/ismvl/ismvl2009.html#DatlaTHH09 %@ 978-0-7695-3607-1

@inproceedings{conf/ismvl/DatlaTHH09, added-at = {2023-03-23T00:00:00.000+0100}, author = {Datla, Satyendra R. and Thornton, Mitchell A. and Hendrix, Luther and Henderson, Dave}, biburl = {https://www.bibsonomy.org/bibtex/21e30b6bffd946f5f309a899c7b9bacac/dblp}, booktitle = {ISMVL}, crossref = {conf/ismvl/2009}, ee = {https://www.wikidata.org/entity/Q62513223}, interhash = {a86ff190f56c5cfe0b97228a143258e4}, intrahash = {1e30b6bffd946f5f309a899c7b9bacac}, isbn = {978-0-7695-3607-1}, keywords = {dblp}, pages = {256-261}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T17:17:41.000+0200}, title = {Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©.}, url = {http://dblp.uni-trier.de/db/conf/ismvl/ismvl2009.html#DatlaTHH09}, year = 2009 }