%0 Journal Article %1 journals/tcas/LiuXYMY15 %A Liu, Jinqi %A Xing, Qianjian %A Yin, Xiaobo %A Mao, Xiubin %A Yu, Feng %D 2015 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 11 %P 1083-1087 %T Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm. %U http://dblp.uni-trier.de/db/journals/tcas/tcasII62.html#LiuXYMY15 %V 62-II

@article{journals/tcas/LiuXYMY15, added-at = {2022-03-21T00:00:00.000+0100}, author = {Liu, Jinqi and Xing, Qianjian and Yin, Xiaobo and Mao, Xiubin and Yu, Feng}, biburl = {https://www.bibsonomy.org/bibtex/26bb3eb7f782ad6fc0a251ba7f93d8858/dblp}, ee = {https://doi.org/10.1109/TCSII.2015.2456371}, interhash = {a8f6b1aaad326476b5797bdc778c8f71}, intrahash = {6bb3eb7f782ad6fc0a251ba7f93d8858}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 11, pages = {1083-1087}, timestamp = {2024-04-09T06:12:55.000+0200}, title = {Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII62.html#LiuXYMY15}, volume = {62-II}, year = 2015 }