%0 Conference Paper %1 conf/ches/SuzukiSI05 %A Suzuki, Daisuke %A Saeki, Minoru %A Ichikawa, Tetsuya %B CHES %D 2005 %E Rao, Josyula R. %E Sunar, Berk %I Springer %K dblp %P 366-382 %T DPA Leakage Models for CMOS Logic Circuits. %U http://dblp.uni-trier.de/db/conf/ches/ches2005.html#SuzukiSI05 %V 3659 %@ 3-540-28474-5

@inproceedings{conf/ches/SuzukiSI05, added-at = {2017-05-21T00:00:00.000+0200}, author = {Suzuki, Daisuke and Saeki, Minoru and Ichikawa, Tetsuya}, biburl = {https://www.bibsonomy.org/bibtex/2c877faf5d89cc8b2ca69d08b1ff19180/dblp}, booktitle = {CHES}, crossref = {conf/ches/2005}, editor = {Rao, Josyula R. and Sunar, Berk}, ee = {https://doi.org/10.1007/11545262_27}, interhash = {1a96b401813420f09f47e45b3b1a2e45}, intrahash = {c877faf5d89cc8b2ca69d08b1ff19180}, isbn = {3-540-28474-5}, keywords = {dblp}, pages = {366-382}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2019-05-15T16:03:00.000+0200}, title = {DPA Leakage Models for CMOS Logic Circuits.}, url = {http://dblp.uni-trier.de/db/conf/ches/ches2005.html#SuzukiSI05}, volume = 3659, year = 2005 }