%0 Journal Article %1 journals/tcad/YuBLRC16 %A Yu, Cunxi %A Brown, Walter %A Liu, Duo %A Rossi, André %A Ciesielski, Maciej J. %D 2016 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 12 %P 2131-2142 %T Formal Verification of Arithmetic Circuits by Function Extraction. %U http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#YuBLRC16 %V 35

@article{journals/tcad/YuBLRC16, added-at = {2022-10-02T00:00:00.000+0200}, author = {Yu, Cunxi and Brown, Walter and Liu, Duo and Rossi, André and Ciesielski, Maciej J.}, biburl = {https://www.bibsonomy.org/bibtex/298e6d0a068c281a124b85a6851979e63/dblp}, ee = {https://doi.org/10.1109/TCAD.2016.2547898}, interhash = {b3f8ad438d1cd6d186f5a875ffffd173}, intrahash = {98e6d0a068c281a124b85a6851979e63}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 12, pages = {2131-2142}, timestamp = {2024-04-08T19:46:35.000+0200}, title = {Formal Verification of Arithmetic Circuits by Function Extraction.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#YuBLRC16}, volume = 35, year = 2016 }