%0 Conference Paper %1 conf/sensys/SuttonZFLGGFBT15 %A Sutton, Felix %A Zimmerling, Marco %A Forno, Reto Da %A Lim, Roman %A Gsell, Tonio %A Giannopoulou, Georgia %A Ferrari, Federico %A Beutel, Jan %A Thiele, Lothar %B SenSys %D 2015 %E Song, Junehwa %E Abdelzaher, Tarek F. %E Mascolo, Cecilia %I ACM %K %P 267-280 %T Bolt: A Stateful Processor Interconnect. %U http://dblp.uni-trier.de/db/conf/sensys/sensys2015.html#SuttonZFLGGFBT15 %@ 978-1-4503-3631-4

@inproceedings{conf/sensys/SuttonZFLGGFBT15, added-at = {2023-12-13T07:06:13.000+0100}, author = {Sutton, Felix and Zimmerling, Marco and Forno, Reto Da and Lim, Roman and Gsell, Tonio and Giannopoulou, Georgia and Ferrari, Federico and Beutel, Jan and Thiele, Lothar}, biburl = {https://www.bibsonomy.org/bibtex/258fb8386e396951403131d3ffb886f59/admin}, booktitle = {SenSys}, crossref = {conf/sensys/2015}, editor = {Song, Junehwa and Abdelzaher, Tarek F. and Mascolo, Cecilia}, ee = {http://doi.acm.org/10.1145/2809695.2809706}, interhash = {b52a8a4812d6b0c7c3d3793308c5f3be}, intrahash = {58fb8386e396951403131d3ffb886f59}, isbn = {978-1-4503-3631-4}, keywords = {}, pages = {267-280}, publisher = {ACM}, timestamp = {2023-12-13T07:06:13.000+0100}, title = {Bolt: A Stateful Processor Interconnect.}, url = {http://dblp.uni-trier.de/db/conf/sensys/sensys2015.html#SuttonZFLGGFBT15}, year = 2015 }