%0 Journal Article %1 journals/tcad/RestleRWP01 %A Restle, Phillip J. %A Ruehli, Albert E. %A Walker, Steven G. %A Papadopoulos, George %D 2001 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 7 %P 877-886 %T Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. %U http://dblp.uni-trier.de/db/journals/tcad/tcad20.html#RestleRWP01 %V 20

@article{journals/tcad/RestleRWP01, added-at = {2022-02-25T00:00:00.000+0100}, author = {Restle, Phillip J. and Ruehli, Albert E. and Walker, Steven G. and Papadopoulos, George}, biburl = {https://www.bibsonomy.org/bibtex/2c8ba4ca107617aea4c8823d2e423883c/dblp}, ee = {https://doi.org/10.1109/43.931029}, interhash = {b538f1e28e093b66ed4175919547f29f}, intrahash = {c8ba4ca107617aea4c8823d2e423883c}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 7, pages = {877-886}, timestamp = {2024-04-08T19:45:40.000+0200}, title = {Full-wave PEEC time-domain method for the modeling of on-chipinterconnects.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad20.html#RestleRWP01}, volume = 20, year = 2001 }