%0 Conference Paper %1 conf/dac/Ulrich83 %A Ulrich, Ernst G. %B DAC %D 1983 %E Radke, Charles E. %I ACM/IEEE %K dblp %P 709-712 %T A design verification methodology based on concurrent simulation and clock suppression. %U http://dblp.uni-trier.de/db/conf/dac/dac1983.html#Ulrich83 %@ 0-8186-0026-8

@inproceedings{conf/dac/Ulrich83, added-at = {2015-11-17T00:00:00.000+0100}, author = {Ulrich, Ernst G.}, biburl = {https://www.bibsonomy.org/bibtex/226289bf4507ea73bd3365551dc746bbd/dblp}, booktitle = {DAC}, crossref = {conf/dac/1983}, editor = {Radke, Charles E.}, ee = {http://dl.acm.org/citation.cfm?id=800747}, interhash = {b6db6dc9db7993adc7cc2a1e748242e5}, intrahash = {26289bf4507ea73bd3365551dc746bbd}, isbn = {0-8186-0026-8}, keywords = {dblp}, pages = {709-712}, publisher = {ACM/IEEE}, timestamp = {2015-11-18T11:55:44.000+0100}, title = {A design verification methodology based on concurrent simulation and clock suppression.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac1983.html#Ulrich83}, year = 1983 }