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%0 Conference Paper
%1 conf/fpl/LuoWYMMFC17
%A Luo, Yingyi
%A Wen, Xianshan
%A Yoshii, Kazutomo
%A Memik, Seda Ogrenci
%A Memik, Gokhan
%A Finkel, Hal
%A Cappello, Franck
%B FPL
%D 2017
%E Santambrogio, Marco D.
%E Göhringer, Diana
%E Stroobandt, Dirk
%E Mentens, Nele
%E Nurmi, Jari
%I IEEE
%K dblp
%P 1-4
%T Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.
%U http://dblp.uni-trier.de/db/conf/fpl/fpl2017.html#LuoWYMMFC17
%@ 978-9-0903-0428-1
@inproceedings{conf/fpl/LuoWYMMFC17,
added-at = {2017-10-11T00:00:00.000+0200},
author = {Luo, Yingyi and Wen, Xianshan and Yoshii, Kazutomo and Memik, Seda Ogrenci and Memik, Gokhan and Finkel, Hal and Cappello, Franck},
biburl = {https://www.bibsonomy.org/bibtex/2ee1c186940431c8ce633e7e89ccd1068/dblp},
booktitle = {FPL},
crossref = {conf/fpl/2017},
editor = {Santambrogio, Marco D. and Göhringer, Diana and Stroobandt, Dirk and Mentens, Nele and Nurmi, Jari},
ee = {https://doi.org/10.23919/FPL.2017.8056827},
interhash = {b88cf0edc3cdb3274a2d1b3a3831e34b},
intrahash = {ee1c186940431c8ce633e7e89ccd1068},
isbn = {978-9-0903-0428-1},
keywords = {dblp},
pages = {1-4},
publisher = {IEEE},
timestamp = {2019-10-17T19:13:11.000+0200},
title = {Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.},
url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2017.html#LuoWYMMFC17},
year = 2017
}