%0 Journal Article %1 journals/mam/ZhouOLL22 %A Zhou, Wu %A Ouyang, Yiming %A Lu, Yingchun %A Liang, Huaguo %D 2022 %J Microprocess. Microsystems %K dblp %P 104464 %T A router architecture with dual input and dual output channels for Networks-on-Chip. %U http://dblp.uni-trier.de/db/journals/mam/mam90.html#ZhouOLL22 %V 90

@article{journals/mam/ZhouOLL22, added-at = {2023-05-17T00:00:00.000+0200}, author = {Zhou, Wu and Ouyang, Yiming and Lu, Yingchun and Liang, Huaguo}, biburl = {https://www.bibsonomy.org/bibtex/26f7b40d7731fa0ff651542cfc6f431e3/dblp}, ee = {https://doi.org/10.1016/j.micpro.2022.104464}, interhash = {ba89722c0bf658925b3e391acd863db2}, intrahash = {6f7b40d7731fa0ff651542cfc6f431e3}, journal = {Microprocess. Microsystems}, keywords = {dblp}, month = {April}, pages = 104464, timestamp = {2024-04-08T19:07:06.000+0200}, title = {A router architecture with dual input and dual output channels for Networks-on-Chip.}, url = {http://dblp.uni-trier.de/db/journals/mam/mam90.html#ZhouOLL22}, volume = 90, year = 2022 }