Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.
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%0 Journal Article
%1 journals/jssc/NingITVHMRT16
%A Ning, Sheyang
%A Iwasaki, Tomoko Ogura
%A Tanakamaru, Shuhei
%A Viviani, Darlene
%A Huang, Henry
%A Manning, Monte
%A Rueckes, Thomas
%A Takeuchi, Ken
%D 2016
%J IEEE J. Solid State Circuits
%K dblp
%N 8
%P 1938-1951
%T Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#NingITVHMRT16
%V 51
@article{journals/jssc/NingITVHMRT16,
added-at = {2020-08-30T00:00:00.000+0200},
author = {Ning, Sheyang and Iwasaki, Tomoko Ogura and Tanakamaru, Shuhei and Viviani, Darlene and Huang, Henry and Manning, Monte and Rueckes, Thomas and Takeuchi, Ken},
biburl = {https://www.bibsonomy.org/bibtex/26850aef0c315099ea473305229d9272c/dblp},
ee = {https://doi.org/10.1109/JSSC.2016.2561966},
interhash = {bb01170c3ff6640816632e7ac03d4155},
intrahash = {6850aef0c315099ea473305229d9272c},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 8,
pages = {1938-1951},
timestamp = {2020-08-31T11:43:09.000+0200},
title = {Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#NingITVHMRT16},
volume = 51,
year = 2016
}
