%0 Conference Paper %1 conf/vlsid/MandalGD02 %A Mandal, Rituparna %A Goswami, Dibyendu %A Dash, Arup %B ASP-DAC/VLSI Design %D 2002 %I IEEE Computer Society %K dblp %P 655-660 %T Reducing Library Development Cycle Time through an Optimum Layout Create Flow. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#MandalGD02 %@ 0-7695-1299-2

@inproceedings{conf/vlsid/MandalGD02, added-at = {2022-11-14T00:00:00.000+0100}, author = {Mandal, Rituparna and Goswami, Dibyendu and Dash, Arup}, biburl = {https://www.bibsonomy.org/bibtex/2d707f5d0b5829c0b6292d77240c90ed7/dblp}, booktitle = {ASP-DAC/VLSI Design}, crossref = {conf/vlsid/2002}, ee = {https://dl.acm.org/doi/10.5555/832284.835442}, interhash = {bb3631f0375ddd28ea23b8e7a49c1cd4}, intrahash = {d707f5d0b5829c0b6292d77240c90ed7}, isbn = {0-7695-1299-2}, keywords = {dblp}, pages = {655-660}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:13.000+0200}, title = {Reducing Library Development Cycle Time through an Optimum Layout Create Flow.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#MandalGD02}, year = 2002 }