Inproceedings,
Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.
F. Abouzeid, A. Bienfait, K. Akyel, S. Clerc, L. Ciampolini, and P. Roche.ESSCIRC, page 205-208. IEEE, (2013)
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- conf/esscirc/AbouzeidBACCR13
- entry type
- inproceedings
- booktitle
- ESSCIRC
- year
- 2013
- pages
- 205-208
- publisher
- IEEE
- crossref
- conf/esscirc/2013
- ee
- https://doi.org/10.1109/ESSCIRC.2013.6649108
- isbn
- 978-1-4799-0644-4
- url
- http://dblp.uni-trier.de/db/conf/esscirc/esscirc2013.html#AbouzeidBACCR13
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%1 conf/esscirc/AbouzeidBACCR13
%A Abouzeid, Fady
%A Bienfait, Audrey
%A Akyel, Kaya Can
%A Clerc, Sylvain
%A Ciampolini, Lorenzo
%A Roche, Philippe
%B ESSCIRC
%D 2013
%I IEEE
%K dblp
%P 205-208
%T Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.
%U http://dblp.uni-trier.de/db/conf/esscirc/esscirc2013.html#AbouzeidBACCR13
%@ 978-1-4799-0644-4
@inproceedings{conf/esscirc/AbouzeidBACCR13,
added-at = {2022-04-09T00:00:00.000+0200},
author = {Abouzeid, Fady and Bienfait, Audrey and Akyel, Kaya Can and Clerc, Sylvain and Ciampolini, Lorenzo and Roche, Philippe},
biburl = {https://www.bibsonomy.org/bibtex/22564c474e1a14b35a2ceb2efc323647b/dblp},
booktitle = {ESSCIRC},
crossref = {conf/esscirc/2013},
ee = {https://doi.org/10.1109/ESSCIRC.2013.6649108},
interhash = {bd7a712cea71f75621c64618f6c66e8a},
intrahash = {2564c474e1a14b35a2ceb2efc323647b},
isbn = {978-1-4799-0644-4},
keywords = {dblp},
pages = {205-208},
publisher = {IEEE},
timestamp = {2024-04-09T17:25:07.000+0200},
title = {Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.},
url = {http://dblp.uni-trier.de/db/conf/esscirc/esscirc2013.html#AbouzeidBACCR13},
year = 2013
}