%0 Conference Paper %1 conf/vlsi/CaffarenaC10 %A Caffarena, Gabriel %A Carreras, Carlos %B VLSI-SoC %D 2010 %I IEEE %K dblp %P 322-327 %T Architectural synthesis of DSP circuits under simultaneous error and time constraints. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2010.html#CaffarenaC10

@inproceedings{conf/vlsi/CaffarenaC10, added-at = {2022-01-03T00:00:00.000+0100}, author = {Caffarena, Gabriel and Carreras, Carlos}, biburl = {https://www.bibsonomy.org/bibtex/2b9dba541d4d75e6fa4788bc83869bd95/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2010soc}, ee = {https://doi.org/10.1109/VLSISOC.2010.5642681}, interhash = {c0ecacd5ff55a8364c7147c5ebdf317f}, intrahash = {b9dba541d4d75e6fa4788bc83869bd95}, keywords = {dblp}, pages = {322-327}, publisher = {IEEE}, timestamp = {2024-04-10T10:16:48.000+0200}, title = {Architectural synthesis of DSP circuits under simultaneous error and time constraints.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2010.html#CaffarenaC10}, year = 2010 }