%0 Conference Paper %1 conf/vlsic/LinTTL16 %A Lin, Ying-Zu %A Tsai, Chih-Hou %A Tsou, Shan-Chih %A Lu, Chao-Hsin %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#LinTTL16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/LinTTL16, added-at = {2016-09-26T00:00:00.000+0200}, author = {Lin, Ying-Zu and Tsai, Chih-Hou and Tsou, Shan-Chih and Lu, Chao-Hsin}, biburl = {https://www.bibsonomy.org/bibtex/2dda0100d9085f1a6c6c27efc4c2d7a5a/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {http://dx.doi.org/10.1109/VLSIC.2016.7573536}, interhash = {c42af60cbe7464fffb5277324b0e9a2a}, intrahash = {dda0100d9085f1a6c6c27efc4c2d7a5a}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2016-09-27T11:36:21.000+0200}, title = {A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#LinTTL16}, year = 2016 }