%0 Journal Article %1 journals/tvlsi/RedifK15 %A Redif, Soydan %A Kasap, Server %D 2015 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 454-465 %T Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#RedifK15 %V 23

@article{journals/tvlsi/RedifK15, added-at = {2023-08-28T00:00:00.000+0200}, author = {Redif, Soydan and Kasap, Server}, biburl = {https://www.bibsonomy.org/bibtex/28697bce66d992860ead6d6e7a00c4a8a/dblp}, ee = {https://www.wikidata.org/entity/Q114083519}, interhash = {c9d180a27529e722e0216fa216fa3b47}, intrahash = {8697bce66d992860ead6d6e7a00c4a8a}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {454-465}, timestamp = {2024-04-08T14:33:16.000+0200}, title = {Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#RedifK15}, volume = 23, year = 2015 }