%0 Journal Article %1 journals/access/MaLLA17 %A Ma, Liang %A Lavagno, Luciano %A Lazarescu, Mihai Teodor %A Arif, Arslan %D 2017 %J IEEE Access %K dblp %P 18953-18974 %T Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis. %U http://dblp.uni-trier.de/db/journals/access/access5.html#MaLLA17 %V 5

@article{journals/access/MaLLA17, added-at = {2018-11-02T00:00:00.000+0100}, author = {Ma, Liang and Lavagno, Luciano and Lazarescu, Mihai Teodor and Arif, Arslan}, biburl = {https://www.bibsonomy.org/bibtex/2ed18431560c2dd15f350d3b5330a9d30/dblp}, ee = {https://doi.org/10.1109/ACCESS.2017.2750923}, interhash = {c9efb600c3c45bc1298293a136c2b1f5}, intrahash = {ed18431560c2dd15f350d3b5330a9d30}, journal = {IEEE Access}, keywords = {dblp}, pages = {18953-18974}, timestamp = {2018-11-03T11:37:48.000+0100}, title = {Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis.}, url = {http://dblp.uni-trier.de/db/journals/access/access5.html#MaLLA17}, volume = 5, year = 2017 }