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%0 Conference Paper
%1 conf/rtas/TrillaJFAC16
%A Trilla, David
%A Jalle, Javier
%A Fernández, Mikel
%A Abella, Jaume
%A Cazorla, Francisco J.
%B RTAS
%D 2016
%I IEEE Computer Society
%K dblp
%P 305-316
%T Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems.
%U http://dblp.uni-trier.de/db/conf/rtas/rtas2016.html#TrillaJFAC16
%@ 978-1-4673-8641-8
@inproceedings{conf/rtas/TrillaJFAC16,
added-at = {2023-03-23T00:00:00.000+0100},
author = {Trilla, David and Jalle, Javier and Fernández, Mikel and Abella, Jaume and Cazorla, Francisco J.},
biburl = {https://www.bibsonomy.org/bibtex/2b8e9b938d900eb535399d9a5eb903a65/dblp},
booktitle = {RTAS},
crossref = {conf/rtas/2016},
ee = {https://doi.ieeecomputersociety.org/10.1109/RTAS.2016.7461338},
interhash = {cab797ebdc39e903740d7079925709df},
intrahash = {b8e9b938d900eb535399d9a5eb903a65},
isbn = {978-1-4673-8641-8},
keywords = {dblp},
pages = {305-316},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T03:27:38.000+0200},
title = {Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems.},
url = {http://dblp.uni-trier.de/db/conf/rtas/rtas2016.html#TrillaJFAC16},
year = 2016
}