%0 Conference Paper %1 conf/ispa/AbderazekSYS03 %A Abderazek, Ben A. %A Shigeta, Soichi %A Yoshinaga, Tsutomu %A Sowa, Masahiro %B ISPA %D 2003 %E Guo, Minyi %E Yang, Laurence Tianruo %I Springer %K dblp %P 248-262 %T On the Design of a Register Queue Based Processor Architecture (FaRM-rq). %U http://dblp.uni-trier.de/db/conf/ispa/ispa2003.html#AbderazekSYS03 %V 2745 %@ 3-540-40523-2

@inproceedings{conf/ispa/AbderazekSYS03, added-at = {2020-12-29T00:00:00.000+0100}, author = {Abderazek, Ben A. and Shigeta, Soichi and Yoshinaga, Tsutomu and Sowa, Masahiro}, biburl = {https://www.bibsonomy.org/bibtex/28329d0434a670d8de00e868df308934c/dblp}, booktitle = {ISPA}, crossref = {conf/ispa/2003}, editor = {Guo, Minyi and Yang, Laurence Tianruo}, ee = {https://doi.org/10.1007/3-540-37619-4_26}, interhash = {cb40e05a591d01bdd120e882d3a28b79}, intrahash = {8329d0434a670d8de00e868df308934c}, isbn = {3-540-40523-2}, keywords = {dblp}, pages = {248-262}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2024-04-10T20:48:16.000+0200}, title = {On the Design of a Register Queue Based Processor Architecture (FaRM-rq).}, url = {http://dblp.uni-trier.de/db/conf/ispa/ispa2003.html#AbderazekSYS03}, volume = 2745, year = 2003 }